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1 revision 1.5 fujitsu semiconductor data sheet prelim i nary 8-bit proprietary microcontroller cmos f 2 mc-8l mb89490 series mb89497/498/f499/pv490 description the mb89490 series has been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit single-chip microcontrollers. in addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as 21-bit timebase timer, watch prescaler, pwm timer, 8/16-bit timer/counter, remote receiver control, lcd controller/driver, external interrupt 0 (edge), external interrupt 1 (level), 10-bit a/d converter, uart/sio, sio, i 2 c and watchdog timer reset. the mb89490 series is designed suitable for compact disc/cassette tape/radio receiver controller as well as in a wide range of applications for consumer product. *: f 2 mc stands for fujitsu flexible microcontroller. features ? package used qfp package for mb89f499, mb89497,mb89498 mqfp package for mb89pv490 high speed operating capa bility at low voltage minimum execution time: 0.32 s/12.5mhz (continued) package (fpt-100p-m06) (ftp-100p-m06) 100-pin plastic qfp (mqp-100c-p01) 100-pin ceramic mqfp
2 mb89490 series (continued) f 2 mc-8l family cpu core clock embedded pll clock multiplication circuit for sub-clock operating clock (pll for sub-clock) can be selected four times of the sub-clock oscillation six timers pwm timer x 2 8/16-bit timer/counter x 2 21-bit timebase timer watch prescaler external interrupt edge detection (selectable edge) : 8 channels low level interrupt (wake-up function) : 8 channels 10-bit a/d converter (8 channels) 10-bit successive approximation type uart/sio synchronous/asynchronous dat a transfer capability sio synchronous data transfer capability lcd controller/driver max. 32 segments output x 4 commons i 2 c interface circuit remote receiver circuit low-power consumption mode stop mode (oscillation stops so as to minimize the current consumption.) sleep mode (cpu stops so as to reduce the current consumption to approx. 1/3 of normal.) watch mode (everything except the watch prescaler stops so as to reduce the power comsumption to an extremely low level.) sub-clock mode watchdog timer reset i/o ports: max. 66channels product lineup mb89497 mb89498 mb89f499 mb89pv490 classification mass production products (mask rom product) flash piggy-back rom size 32k x 8-bit (internal rom) 48k x 8-bit (internal rom) 60k x 8-bit (internal flash) 60k x 8-bit (external rom)* 1 ram size 1k x 8-bit 2k x 8-bit 2k x 8-bit 2k 8-bit *1 : use mbm27c512 as the external rom. multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. instruction set optimized for controllers part numbe r parameter
3 mb89490 series *1 : i 2 c is complied to philips i 2 c specification. mb89497 mb89498 mb89f499 mb89pv490 cpu functions number of instructions : 136 instruction bit length : 8 bits instruction length : 1 to 3 bytes data bit length : 1, 8, 16 bits minimum execution time : 0.32 s/12.5 mhz minimum interrupt processing time : 2.88 s/12.5 mhz ports i/o ports (cmos) : 56 pins input ports (cmos) : 2 pins n-channel open drain i/o ports : 8 pins total : 66 pins 21-bit timebase timer interrupt period (0.66 ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 mhz watchdog timer reset period (167.8 ms to 335.5 ms) at 12.5 mhz. pwm timer 0,1 8-bit reload timer operation (supports square wave output, operating clock period: 1, 8, 16, 64 t inst ,) 8-bit resolution pwm operation 8/16-bit timer/ counter 00, 01 can be operated either as a 2-channel 8-bit timer/counter (timer 00 and timer 01, each with its own independent operating clock cycle), or as one 16-bit timer/counter in timer 00 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capability 8/16-bit timer/ counter 10, 11 can be operated either as a 2-channel 8-bit timer/counter (timer 10 and timer 11, each with its own independent operating clock cycle), or as one 16-bit timer/counter in timer 10 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capability external interrupt 0 (edge) 8 independent channels (selectable edge, interrupt vector, request flag) external interrupt 1 (level) 8 channels (low level interrupt) a/d converter 10-bit resolution 8 channels a/d conversion function (conversion time: 38 t inst ) supports repeated activation by internal clock lcd controller/driver common output : 4 (max.) segment output : 32 (max.) bias power supply pins : 3 lcd display ram size : 32 4 bits uart/sio synchronous/asynchronous data transfer capability (max. baud rate: 97.656 kbps at 12.5 mhz) (7 and 8 bits with parity bit; 8 and 9 bits without parity bit) sio 8-bit serial i/o with lsb first/msb first selectability one clock selectable from four operation clock (one external shift clock, three internal shift clock: 0.64 s, 2.56 s, 10.24 s at 12.5mhz) i 2 c *1 1 channel use a 2-wire protocol to communicate with other device remote receiver selectable maximum noise width removal reversible input polarity standby mode sleep mode, stop mode, watch mode, sub-clock mode process cmos operating voltage 2.2v ~ 3.6v 2.7v ~ 3.6v 2.7v ~ 3.6v part numbe r parameter
4 mb89490 series package and corresponding products o : availabe x : not available differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following point: the stack area is set at the upper limit of the ram. 2. current consumption for the mb89pv490 the current consumed by the eprom mounted in the piggy-back socket is needed to be included. when operating at low speed, the current consumed by the flash product is greater than that for the mask rom product. however, the current consumption is roughly the same in sleep and stop mode. for more information, see ? electrical characteristics.? 3. oscillation stabilization time after power-on reset for mb89pv490 and mb89f499, the power-on stabilization time cannot be selected. for mb89497 and mb89498, the power-on stabilization time can be selected. for more information, please refer to ? mask option?. part number package mb89497/498 mb89f499 mb89pv490 fpt-100p-m06 o o x mqp-100c-p01 x x o
5 mb89490 series pin assignment ( fpt-100p-m06) vcc *p00 *p01 *p02 *p03 *p04 *p05 *p06 *p07 p10/int00 p11/int01 p12/int02 p13/int03 p14/int04 p15/int05 p16/int06 p17/int07 p20/to0 p21/rmc p22/ec0 p23 p24/to1 p25/ec1 p26/pwm0 p27/pwm1 p50/si0 p51/so0 p52/sck0 avr avcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 avss p30/an0/int10 p31/an1/int11 p32/an2/int12 p33/an3/int13 p34/an4/int14 p35/an5/int15 p36/an6/int16 p37/an7/int17 *p40 *p41 *p42 *p43 *p44 *p45 *p46/scl *p47/sda x1a x0a vss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p65/seg21 p64/seg20 p63/seg19 p62/seg18 p61/seg17 p60/seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 p54/com3 p53/com2 com1 com0 v1 v2 v3 vcc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vss x0 x1 mod0 rst p84 p83 p82/sck1 p81/so1 p80/si1 p77/seg31 p76/seg30 p75/seg29 p74/seg28 p73/seg27 p72/seg26 p71/seg25 p70/seg24 p67/seg23 p66/seg22 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 (top view) * high current pins
6 mb89490 series ( mqp-100c-p01) vcc *p00 *p01 *p02 *p03 *p04 *p05 *p06 *p07 p10/int00 p11/int01 p12/int02 p13/int03 p14/int04 p15/int05 p16/int06 p17/int07 p20/to0 p21/rmc p22/ec0 p23 p24/to1 p25/ec1 p26/pwm0 p27/pwm1 p50/si0 p51/so0 p52/sck0 avr avcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 avss p30/an0/int10 p31/an1/int11 p32/an2/int12 p33/an3/int13 p34/an4/int14 p35/an5/int15 p36/an6/int16 p37/an7/int17 *p40 *p41 *p42 *p43 *p44 *p45 *p46/scl *p47/sda x1a x0a vss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p65/seg21 p64/seg20 p63/seg19 p62/seg18 p61/seg17 p60/seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 p54/com3 p53/com2 com1 com0 v1 v2 v3 vcc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vss x0 x1 mod0 rst p84 p83 p82/sck1 p81/so1 p80/si1 p77/seg31 p76/seg30 p75/seg29 p74/seg28 p73/seg27 p72/seg26 p71/seg25 p70/seg24 p67/seg23 p66/seg22 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 (top view) * high current pins 121 122 123 124 125 126 127 128 129 113 112 111 110 109 108 107 106 105 130 131 132 101 102 103 104 120 119 118 117 116 115 114 pin assignment on package top (mb89pv490 only) n.c.: as connected internally, do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 101 n.c. 109 a2 117 n.c. 125 oe 102 a15 110 a1 118 o4 126 n.c. 103 a12 111 a0 119 o5 127 a11 104 a7 112 n.c. 120 o6 128 a9 105 a6 113 o1 121 o7 129 a8 106 a5 114 o2 122 o8 130 a13 107 a4 115 o3 123 ce 131 a14 108 a3 116 v ss 124 a10 132 v cc
7 mb89490 series pin description pin number pin name i/o circuit type function mqfp* 1 /qfp* 2 99 x0 a connection pins for a crystal or other oscillator. an external clock can be connected to x0. in this case, leave x1 open. 98 x1 49 x0a a connection pins for a crystal or other oscillator. an external clock can be connected to x0a. in this case, leave x1a open. 48 x1a 97 mod0 b input pin for setting the memory access mode. connect directly to v ss . 95, 94 p84,p83 j general-purpose cmos input port. 96 rst c reset i/o pin. the pin is an n-ch open-drain type with pull-up resistor and a hysteresis input. the pin outputs an ?l? level when an internal reset request is present. inputting an ?l? level initializes internal circuits. 2~9 p00 ~ p07 d general-purpose cmos i/o port. 10~17 p10/int00 ~ p17/int07 e general-purpose cmos i/o port. the pin is shared with external interrupt 0 input. 18 p20/to0 f general-purpose cmos i/o port. the pin is shared with 8/16-bit timer/counter 00, 01 output. 19 p21/rmc e general-purpose cmos i/o port. the pin is shared with remote receiver input. 20 p22/ec0 e general-purpose cmos i/o port. the pin is shared with 8/16-bit timer/counter 00, 01 input. 21 p23 f general-purpose cmos i/o port. 22 p24/to1 f general-purpose cmos i/o port. the pin is shared with 8/16-bit timer/counter 10, 11 output. 23 p25/ec1 e general-purpose cmos i/o port. the pin is shared with 8/16-bit timer/counter 10,11 input. 24 p26/pwm0 f general-purpose cmos i/o port. the pin is shared with pwm0 output. 25 p27/pwm1 f general-purpose cmos i/o port. the pin is shared with pwm1 output. 32 ~ 39 p30/an0/int10 ~ p37/an7/int17 g general-purpose cmos i/o port. the pin is shared with external interrupt 1 input and a/d converter input. 40 ~ 45 p40~p45 h general-purpose n-ch open-drain i/o port. 46 p46/scl h general-purpose n-ch open-drain i/o port. the pin is shared with i2c clock i/o. 47 p47/sda h general-purpose n-ch open-drain i/o port. the pin is shared with i2c data i/o. 26 p50/si0 e general-purpose cmos i/o port. the pin is shared with sio data input. 27 p51/so0 f general-purpose cmos i/o port. the pin is shared with sio data output. 28 p52/sck0 e general-purpose cmos i/o port. the pin is shared with sio clock i/o.
8 mb89490 series (continued) *1: mqp-100c-p01 *2: fpt-100p-m06 pin number pin name i/o circuit type function mqfp* 1 /qfp* 2 57 p53/com2 f / i general-purpose cmos i/o port. the pin is shared with the lcd common output. 58 p54/com3 f / i general-purpose cmos i/o port. the pin is shared with the lcd common output. 75 ~ 82 p60/seg16 ~ p67/seg23 f / i general-purpose cmos i/o port. the pin is shared with lcd segment output. 83 ~ 90 p70/seg24 ~ p77/seg31 f / i general-purpose cmos i/o port. the pin is shared with lcd segment output. 91 p80/si1 e general-purpose cmos i/o port. the pin is shared with uart/sio data input. 92 p81/so1 f general-purpose cmos i/o port. the pin is shared with uart/sio data output. 93 p82/sck1 e general-purpose cmos i/o port. the pin is shared with uart/sio clock i/o. 59 ~ 74 seg0 ~ seg15 i lcd segment output-only pin. 55 ~ 56 com0 ~ com1 i lcd common output-only pin. 54, 53, 52 v1 to v3 ? lcd driving power supply pin. 1,51 v cc ? power supply pin. 50,100 v ss ? power supply pin (gnd). 30 av cc ? a/d converter power supply pin. 29 avr ? a/d converter reference voltage input pin. 31 av ss ? a/d converter power supply pin. use at the same voltage level as v ss .
9 mb89490 series ? external eprom socket (mb89pv490 only) *1: mqp-100c-p01 pin number pin name i/o function mqfp* 1 102 131 130 103 127 124 128 129 104 105 106 107 108 109 110 111 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins. 122 121 120 119 118 115 114 113 o8 o7 o6 o5 o4 o3 o2 o1 i data input pins. 101 112 117 126 n.c. ? internally connected pins. always leave open. 116 v ss o power supply pin (gnd). 123 ce o chip enable pin for the eprom. outputs ?h? in standby mode. 125 oe o output enable pin for the eprom. always outputs ?l?. 132 v cc o power supply pin for the eprom.
10 mb89490 series i/o circuit type (continued) circuit class circuit remarks a main/sub-clock circuit b hysteresis input (cmos input in mb89f499) the pull-down resistor (not available in mb89f499) approx. 50k ? c the pull-up resistor (p-channel) approx. 50 k ? hysteresis input d cmos output ioh=-4ma, iol=12ma cmos input selectable pull-up resistor approx. 50 k ? e cmos output ioh=-2ma, iol=4ma cmos port input hysteresis resource input selectable pull-up resistor approx. 50 k ? x1 (x1a) x0 (x0a) n-ch p-ch p-ch n-ch stop mode control signal n-ch r p-ch n-ch r p-ch n-ch r port pull-up resistor register p-ch p-ch n-ch r port resource pull-up resistor register p-ch
11 mb89490 series (continued) (continued) f cmos output ioh=-2ma, iol=4ma cmos input selectable pull-up resistor approx. 50 k ? g cmos output ioh=-2ma, iol=4ma cmos port input automotive (vih=0.85vcc, vil=0.5vcc) resource input analog input selectable pull-up resistor approx. 50 k ? h n-ch open-drain output iol=15ma cmos port input cmos resource input 5v tolerance i lcd segment output j cmos input p-ch n-ch r port pull-up resistor register p-ch p-ch n-ch r port resource pull-up resistor register p-ch analog n-ch port / resource n-ch p-ch p-ch n-ch
12 mb89490 series handling devices 1. preventing latch-up latch-up may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on ?1. absolute maximum ratings? in ? electrical characteristics? is applied between v cc and v ss . when latch-up occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr), and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d connect to be av cc = v cc and av ss = avr = v ss even if the a/d is not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode. 7. treatment of unused dedicated lcd pins when dedicated lcd pins are not in use, keep them open.
13 mb89490 series programming and erasing flash memory on the mb89f499 1. flash memory the flash memory is located between 1000 h and ffff h in the cpu memory map and incorporates a flash memory interface circuit that allows read access and program access from the cpu to be performed in the same way as mask rom. programming and erasing flash memory is also performed via the flash memory interface circuit by executing instructions in the cpu. this enables the flash memory to be updated in place under the control of the cpu, providing an efficient method of updating program and data. 2. flash memory features 60 k byte 8-bit configuration (16 k + 8 k + 8 k + 28 k sectors) automatic programming algorithm (embedded algorithm* : equivalent to mbm29lv200) includes an erase pause and restart function data polling a nd toggle bit for detection of program/erase completion detection of program/erase completion via cpu interrupt compatible with jedec-standard commands sector protection (sectors can be combined in any combination) no. of program/erase cycles : 10,000 (min) *: embedded algorithm is a trademark of advanced micro devices. 3. procedure for programming and erasing flash memory programming and reading flash memory cannot be performed at the same time. accordingly, to program or erase flash memory, the program must first be copied from flash memory to ram so that programming can be performed without program access from flash memory. 4. flash memory register control status register (fmcs) 5. sector configuration the table below shows the sector configuration of flash memory and lists the addresses of each sector for both during cpu access a flash memory programming. sector configuration of flash memory address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 007a h inte rdyint we rdy reserved reserved ? reserved 000x00-0 b r/w r/w r/w r r/w r/w ? r/w flash memory cpu address programmer address* 16 k bytes ffff h to c000 h 1ffff h to 1c000 h 8 k bytes bfff h to a000 h 1bfff h to 1a000 h 8 k bytes 9fff h to 8000 h 19fff h to 18000 h 28 k bytes 7fff h to 1000 h 17fff h to 11000 h
14 mb89490 series * : programmer address the programmer address is the address to be used instead of the cpu address when programming data from a parallel flash memory programmer. use t he programmer address on programming or erasing using a general purpose parallel programmer. 6. rom programmer adaptor and recommended rom programmers * enquiries sunhayato co. ltd. : fax +81-3-5396-9106 ando denki co. ltd. : tel +81-44-549-7300 part number package adaptor part no. recommended programmer manufacturer and model sun hayato co. ltd. ando denki co. ltd. mb89f499pf fpt-100p-m06 tbd af9708 (ver 1.60 or later) af9709 (ver 1.60 or later)
15 mb89490 series programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c512-20tv 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel 81-3-3986-0403 3. memory space memory space in each mode is shown in the diagram below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c512. (2) load program data into the eprom programmer at 1000 h to ffff h . (3) program to 1000 h to ffff h with the eprom programmer. package adapter socket part number lcc-32 (rectangle) rom-32lc-28dp-yg address normal operating mode corresponding addresses on the eprom programmer 1000 h ffff h 0000 h 0080 h 0880 h 1000 h ffff h i/o ram not available prom 60kb eprom 60kb
16 mb89490 series block diagram main clock clock controller sub-clock ram (1k bytes / 2k bytes) f 2 mc-8l cpu rom (32k bytes / 48k bytes) other pins vcc x 2, vss x 2, mod0 internal data bus 21-bit timebase uart/sio port 8 port 3 x0 x1 p82/sck1 timer x0a x1a port 1 cmos i/o port i2c 8 lcd controller/driver 32 4-bit display ram (16 bytes) port 6, 7 cmos i/o port p54/com3 to p53/com2 seg0 t0 seg15 16 com0 to com1 2 v1 to v3 2 p17/int07 to p10/int00 reset circuit (watchdog timer) rst external interrupt 1 (level) 8 2 16 oscillator oscillator watch prescaler 8/16-bit timer/counter 00,01 cmos i/o port port 2 8/16-bit timer/counter 10,11 p23 p22/ec0 p20/to0 p25/ec1 p24/to1 cmos i/o port external interrupt 0 (edge) 8 p80/si1 p81/so1 10-bit a/d converter p37/an7/int17 to p30/an0/int10 avcc avss avr 8 *1: high current i/o port. cmos i/o port p67/seg23 to p60/seg16 p77/seg31 to p70/seg24 3 6 p45 to p40 n-ch open-drain i/o port port 4 *1 sio p52/sck0 p50/si0 p51/so0 p27/pwm1 p47/sda p46/scl 8-bit pwm timer 0 8 8 8-bit pwm timer 1 p26/pwm0 remote receiver p21/rmc (pll x 1,2,4) port 0 *1 cmos i/o port p07 to p00 8 8 port 5 cmos i/o port p84 p83
17 mb89490 series cpu core 1. memory space the microcontrollers of the mb89490 series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located the lowest addr ess. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89490 series is structured as illustrated below. memory space mb89f499 general- purpose registers i/o ram 0000 h 0080 h 0100 h 0880 h ffff h 0200 h vacant mb89498 general- purpose registers i/o ram rom 0000 h 0080 h 0100 h 0880 h ffff h 0200 h vacant mb89pv490 general- purpose registers i/o ram 0000 h 0080 h 0100 h ffff h 0200 h 0880 h rom external (60k) 1000 h vacant 1000 h 4000 h ffc0 h ffc0 h ffc0 h vector table (reset, interrupt, vector call instruction) mb89497 general- purpose registers i/o ram rom 0000 h 0080 h 0100 h 0480 h ffff h 0200 h vacant 8000 h ffc0 h flash (60k)
18 mb89490 series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions. accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register for performing arithmetic operations with the accumulator. when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification. extra pointer (ep): a 16-bit pointer for indicating a memory address. stack pointer (sp): a 16-bit register for indicating a stack area. program status (ps): a 16-bit register for storing a register pointer, a condition code. the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code r egister (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy vacancy vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr
19 mb89490 series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set to "1" when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. clear to "0" otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to "1". interrupt is prohibited when the flag is set to "0". clear to "0" when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set to "1" if the msb is set to "1" as the result of an arithmetic operation. clear to "0" otherwise. z-flag: set to "1" when an arithmetic operation results in "0". clear to "0" otherwise. v-flag: set to "1" if a signed numeric value overflows because of an arithmetic calculation. clear to "0" if the overflow does not occur. c-flag: set to "1" when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. clear to "0" otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level priority 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ?0? a15 ?0? a14 ?0? a13 ?0? a12 ?0? a11 ?0? a10 ?0? a9 ?1? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
20 mb89490 series the following general-purpose registers are provided: general-purpose registers: an 8- bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers. up to a total of 32 banks can be used on the mb89490 series. the bank currently in use is indicated by the register bank pointer (rp). register bank configuration this address = 0100 h + 8 (rp) memory area 32 banks r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7
21 mb89490 series i/o map (continued) address register name register description read/write initial value 00 h pdr0 port 0 data register r/w xxxxxxxx b 01 h ddr0 port 0 data direction register w* 00000000 b 02 h pdr1 port 1 data register r/w xxxxxxxx b 03 h ddr1 port 1 data direction register w* 00000000 b 04 h pdr2 port 2 data register r/w 00000000 b 05 h (reserved) 06 h ddr2 port 2 data direction register r/w 00000000 b 07 h sycc system clock control register r/w x-1mm100 b 08 h stbc standby control register r/w 00010xxx b 09 h wdtc watchdog timer control register w* 0---xxxx b 0a h tbtc timebase timer control register r/w 00---000 b 0b h wpcr watch prescaler control register r/w 00--0000 b 0c h pdr3 port 3 data register r/w xxxxxxxx b 0d h ddr3 port 3 data direction register r/w 00000000 b 0e h rsfr reset flag register r xxxx---- b 0f h pdr4 port 4 data register r/w 11111111 b 10 h pdr5 port 5 data register r/w ---xxxxx b 11 h ddr5 port 5 data direction register r/w ---00000 b 12 h pdr6 port 6 data register r/w xxxxxxxx b 13 h ddr6 port 6 data direction register r/w 00000000 b 14 h pdr7 port 7 data register r/w xxxxxxxx b 15 h ddr7 port 7 data direction register r/w 00000000 b 16 h pdr8 port 8 data register r/w ---xxxxx b 17 h ddr8 port 8 data direction register r/w ---00000 b 18 h eic0 external interrupt 0 control register 0 r/w 00000000 b 19 h eic1 external interrupt 0 control register 1 r/w 00000000 b 1a h eic2 external interrupt 0 control register 2 r/w 00000000 b 1b h eic3 external interrupt 0 control register 3 r/w 00000000 b 1c h eie1 external interrupt 1 enable register r/w 00000000 b 1d h eif1 external interrupt 1 flag register r/w -------0 b 1e h smr serial mode register r/w 00000000 b 1f h sdr serial data register r/w xxxxxxxx b 20 h t01cr timer 01 control register r/w 000000x0 b 21 h t00cr timer 00 control register r/w 000000x0 b 22 h t01dr timer 01 data register r/w xxxxxxxx b 23 h t00dr timer 00 data register r/w xxxxxxxx b 24 h t11cr timer 11 control register r/w 000000x0 b 25 h t10cr timer 10 control register r/w 000000x0 b
22 mb89490 series (continued) (continued) address register name register description read/write initial value 26 h t11dr timer 11 data register r/w xxxxxxxx b 27 h t10dr timer 10 data register r/w xxxxxxxx b 28 h ader a/d input enable register r/w 11111111 b 29 h adc0 a/d control register 0 r/w -00000x0 b 2a h adc1 a/d control register 1 r/w -0000001 b 2b h addh a/d data register (upper byte) r ------xx b 2c h addl a/d data register (lower byte) r xxxxxxxx b 2d h cntr0 pwm 0 timer control register r/w 0-000000 b 2e h comr0 pwm 0 timer compare register w* xxxxxxxx b 2f h smc0 uart/sio serial mode control register r/w 00000000 b 30 h smc1 uart/sio serial mode control register r/w 00000000 b 31 h ssd uart/sio serial status/data register r/w 00001--- b 32 h sidr/sodr uart/sio serial data register r/w xxxxxxxx b 33 h src uart/sio serial rate control register r/w xxxxxxxx b 34 h cntr1 pwm 1 timer control register r/w 0-000000 b 35 h comr1 pwm 1 timer compare register w* xxxxxxxx b 36 h ibsr i 2 c bus status register r 00000000 b 37 h ibcr i 2 c bus control register r/w 00000000 b 38 h iccr i 2 c clock control register r/w 000xxxxx b 39 h iadr i 2 c address register r/w xxxxxxxx b 3a h idar i 2 c data register r/w xxxxxxxx b 3b h pllcr sub pll control register r/w ----0000 b 3c h to 3f h (reserved) 40 h rmn remote control counter register r xx xxxxxx b 41 h rmc remote control control register r/w 00000000 b 42 h rms remote control status register r/w 0x000001 b 43 h rmd remote control fifo data register r x----xxx b 44 h rmcd0 remote control compare register 0 r/w 11111111 b 45 h rmcd1 remote control compare register 1 r/w 11111111 b 46 h rmcd2 remote control compare register 2 r/w 11111111 b 47 h rmcd3 remote control compare register 3 r/w 11111111 b 48 h rmcd4 remote control compare register 4 r/w 11111111 b 49 h rmcd5 remote control compare register 5 r/w 11111111 b 4a h rmci remote interrupt register r/w -110-000 b 4b h to 5d h (reserved) 5e h locr lcd controller output control register r/w -0000000 b 5f h lcd lcd controller control register r/w 00010000 b 60 h to 6f h vram lcd data ram r/w xxxxxxxx b 70 h purc0 port 0 pull up resistor control register r/w 11111111 b 71 h purc1 port 1 pull up resistor control register r/w 11111111 b
23 mb89490 series (continued) * bit manipulation instruction cannot be used. read/write access symbols r/w : readable and writable r : read-only w : write-only initial value symbols 0: the initial value of this bit is ?0?. 1: the initial value of this bit is ?1?. x: the initial value of this bit is undefined. - : unused bit. m: the initial value of this bit is determined by mask option. address register name register description read/write initial value 72 h purc2 port 2 pull up resistor control register r/w 11111111 b 73 h purc3 port 3 pull up resistor control register r/w 11111111 b 74 h purc5 port 5 pull up resistor control register r/w ---11111 b 75 h purc6 port 6 pull up resistor control register r/w 11111111 b 76 h purc7 port 7 pull up resistor control register r/w 11111111 b 77 h purc8 port 8 pull up resistor control register r/w -----111 b 78 h to 79 h (reserved) 7a h fmcs flash memory control status registger r/w 000x00-0 b 7b h ilr1 interrupt level setting register 1 w* 11111111 b 7c h ilr2 interrupt level setting register 2 w* 11111111 b 7d h ilr3 interrupt level setting register 3 w* 11111111 b 7e h ilr4 interrupt level setting register 4 w* 11111111 b 7f h (reserved)
24 mb89490 series electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) precautions: permanent device damage may occur if the above ?absolute maximum ratings? are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc av cc v ss ? 0.3 v ss + 4.0 v av cc must be equal to v cc avr v ss ? 0.3 v ss + 4.0 v lcd power supply voltage v1 to v3 v ss ? 0.3 v cc v input voltage v i v ss ? 0.3 v cc + 0.3 v other than p40~p47 v ss ? 0.3 v ss + 6.0 v p40~p47 in mb89pv490, mb89497/498 v ss ? 0.3 v ss + 5.5 v p40~p47 in mb89f499 output voltage v o v ss ? 0.3 v cc + 0.3 v ?l? level maximum output current i ol ? 15 ma ?l? level average output current i olav ? 4ma average value (operating current operating rate) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 40 ma average value (operating current operating rate) ?h? level maximum output current i oh ? ?15 ma ?h? level average output current i ohav ? ?4 ma average value (operating current operating rate) ?h? level total maximum output current i oh ? ?50 ma ?h? level total average output current i ohav ? ?20 ma average value (operating current operating rate) power consumption p d ? 300 mw operating temperature t a ?40 +85 c storage temperature tstg ?55 +150 c
25 mb89490 series 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values depend on the operating conditions and the analog assurance range. see figure 1, 2 and ?5. a/d converter electrical characteristics.? figure 1 operating voltage vs. main clock operating frequency (mb89f499/497/498) parameter symbol value unit remarks min. max. power supply voltage v cc av cc 2.7* 3.6 v operation assurance range mb89pv490, mb89f499 2.2* 3.6 v operation assurance range mb89497, mb89498 1.5 3.6 v retains the ram state in stop mode avr 2.7 3.6 v lcd power supply voltage v1 to v3 vss vcc v operating temperature t a ?40 +85 c 2.0 3.0 1.0 2.03.04.05.06.07.08.09.010.0 operating voltage (v) 4.0 2.0 1.0 0.4 1.33 0.8 0.66 0.57 0.50 0.44 3.6 2.7 11.0 12.0 12.5 0.36 0.33 0.32 analog accuracy assurance range : vcc = avcc = 2.7v~3.6v 2.2 min execution time (inst. cycle) ( s) main clock operating freq. (mhz) note : the shaded area is not assured for mb89f499
26 mb89490 series figure 2 operating voltage vs. main clock operating frequency (mb89pv490) figure 1 and 2 indicate the operating frequency of the external oscilla tor at an instruction cycle of 4/f ch . since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 3.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 operating voltage (v) 4.0 2.0 1.0 0.4 1.33 0.8 0.66 0.57 0.50 0.44 main clock operating freq. (mhz) min execution time (inst. cycle) ( s) 3.5 2.7 11.0 12.0 12.5 0.36 0.33 0.32 analog accuracy assurance range : vcc = avcc = 2.7v~3.6v 3.6
27 mb89490 series 3. dc characteristics (av cc = v cc = 3.0 v, av ss = v ss = 0.0 v, t a = ?40 c to +85 c) (continued) parameter symbol pin condition value unit remarks min. typ. max. ?h? level input voltage v ih p00 ~ p07, p10 ~ p17, p20 ~ p27, p30 ~ p37, p50 ~ p54, p60 ~ p67, p70 ~ p77, p80 ~ p84, scl, sda, mod1, mod2 ? 0.7 v cc ?v cc + 0.3 v p40 ~ p47 ? 0.7 v cc ?v ss + 6.0 v mb89pv490, mb89497/498 ? 0.7 v cc ?v ss + 5.5 v mb89f499 v ihs rst , mod0, ec0, ec1, sck0, si0, sck1, si1, rmc, int00 ~ int07 ? 0.8 v cc ?v cc + 0.3 v v iha int10 ~ int17 ?0.85 v cc ?v cc + 0.3 v ?l? level input voltage v il p00 ~ p07, p10 ~ p17, p20 ~ p27, p30 ~ p37, p40 ~ p47, p50 ~ p54, p60 ~ p67, p70 ~ p77, p80 ~ p84, scl, sda, mod1, mod2 ?v ss ? 0.3 ? 0.3 v cc v v ils rst , mod0, ec0, ec1, sck0, si0, sck1, si1, rmc, int00 ~ int07 ?v ss ? 0.3 ? 0.2 v cc v v ila int10 ~ int17 ?v ss ? 0.3 ? 0.5 v cc v open-drain output pin application voltage v d p40 ~ p47 ?v ss ? 0.3 ? v ss + 6.0 v mb89pv490, mb89497/498 ?v ss ? 0.3 ? v ss + 5.5 v mb89f499 ?h? level output voltage v oh p10 ~ p17, p20 ~ p27, p30 ~ p37, p50 ~ p54, p60 ~ p67, p70 ~ p77, p80 ~ p82 i oh = -2.0 ma 2.2 ? ? v p00 ~ p07 i oh = -4.0 ma 2.2 ? ? v
28 mb89490 series (continued) (continued) parameter symbol pin condition value unit remarks min. typ. max. ?l? level output voltage v ol p10 ~ p17, p20 ~ p27, p30 ~ p37, p50 ~ p54, p60 ~ p67, p70 ~ p77, p80 ~ p82, rst i ol = 4.0 ma ? ? 0.4 v p00 ~ p07 i ol = 12.0 ma ? ? 0.4 v p40 ~ p47 i ol = 15.0 ma ? ? 0.4 v input leakage current i li p00 ~ p07, p10 ~ p17, p20 ~ p27, p30 ~ p37, p40 ~ p47, p50 ~ p54, p60 ~ p67, p70 ~ p77, p80 ~ p84 0.45 v < v i < v cc ? 5? + 5 a without pull-up resistor open-drain output leakage current i lod p40 ~ p47 0.0 v < v i < v cc ? 5? + 5 a pull-down resistance r down mod0 v i = v cc 25 50 100 k ? except mb89f499 pull-up resistance r pull p00 ~ p07, p10 ~ p17, p20 ~ p27, p30 ~ p37, p50 ~ p54, p60 ~ p67, p70 ~ p77, p80 ~ p82, rst v i = 0.0 v 25 50 100 k ? when pull-up resistor is selected (except rst ) common output impedance r vcom com0 to com3 v1 to v3 = +3.0 v ? ? 2.5 k ? segment output impedance r vseg seg0 to seg31 v1 to v3 = +3.0 v ? ? 15 k ? lcd divided resistance r lcd ? between v cc and v ss 300 500 750 k ? lcd controller/ driver leakage current i lcdl v1 to v3, com0 to com3, seg0 to seg31 ?-1? + 1 a
29 mb89490 series (continued) parameter symbol pin condition value unit remarks min. typ. max. power supply current i cc1 v cc f ch = 10 mhz t inst = 0.4 s main clock run mode ?3.5tbdma mb89pv490, mb89497/498 ? 6.0 tbd ma mb89f499 i cc2 f ch = 10 mhz t inst = 6.4 s main clock run mode ?0.4tbdma mb89pv490, mb89497/498 ? 1.5 tbd ma mb89f499 i ccs1 f ch = 10 mhz t inst = 0.4 s main clock sleep mode ?1.2tbdma mb89pv490, mb89497/498 ? 2.0 tbd ma mb89f499 i ccs2 f ch = 10 mhz t inst = 6.4 s main clock sleep mode ?0.4tbdma mb89pv490, mb89497/498 ? 1.0 tbd ma mb89f499 i ccl f cl = 32.768 khz sub-clock mode t a = +25 0 c ? 22.0 tbd a mb89pv490, mb89497/498 ? 35.0 tbd a mb89f499 i cclpll f cl = 32.768 khz sub-clock mode t a = +25 0 c sub pll x 4 ? 120.0 tbd a mb89pv490, mb89497/498 ? 150.0 tbd a mb89f499 i ccls f cl = 32.768 khz sub-clock sleep mode t a = +25 0 c ?7.0tbd a mb89pv490, mb89497/498 ? 15.0 tbd a mb89f499 i cct f cl = 32.768 khz watch mode main clock stop mode t a = +25 0 c ?1.0tbd a mb89pv490, mb89497/498 ?5.0tbd a mb89f499 i cch t a = +25 0 c sub-clock stop mode ?0.8tbd a mb89pv490, mb89497/498 ?1.0tbd a mb89f499 i a av cc av cc = 3.0 v, t a = +25 0 c ? 1.0 3.0 ma a/d converting i ah t a = +25 0 c ?0.84.0 a a/d stop input capacitance c in other than v cc , v ss , av cc , av ss, avr f = 1 mhz ? 10.0 ? pf
30 mb89490 series 4. ac characteristics (1) reset timing (av cc = v cc = 3.0 v, av ss = v ss = 0.0 v, t a = ?40 c to +85 c) note: t hcyl is the oscillation cycle (1/f ch ) to input to the x0 pin. the mcu operation is not guaranteed when the "l" pulse width is shorter than t zlzh . (2) power-on reset (av ss = v ss = 0.0 v, t a = ?40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. rapid changes in power supply voltage may cause a power-on reset. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst ?l? pulse width t zlzh ? 48 t hcyl ?ns parameter symbol condition value unit remarks min. max. power supply rising time t r ? ?50ms power supply cut-off time t off 1 ? ms due to repeated operations t zlzh 0.2 v cc 0.2 v cc rst 0.2 v 0.2 v 0.2 v t r v cc t off 1.5 v
31 mb89490 series (3) clock timing (av ss = v ss = 0.0 v, t a = ?40 c to +85 c) parameter symbol pin value unit remarks min. typ. max. clock frequency f ch x0, x1 1 ? 12.5 mhz f cl x0a, x1a ? 32.768 75 khz clock cycle time t hcyl x0, x1 80 ? 1000 ns t lcyl x0a, x1a 13.3 30.5 ? s input clock pulse width p wh p wl x0 20 ? ? ns external clock p whl p wll x0a ? 15.2 ? s input clock rising/falling time t cr t cf x0, x0a ? ? 10 ns 0.2 v cc 0.8 v cc x 0 0.2 v cc t cr p wh t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic reasonator is used when an external clock is used open t hcyl p wl f ch c1 c2 f ch x0 and x1 timing and conditions main clock conditions
32 mb89490 series (4) instruction cycle parameter symbol value unit remarks instruction cycle (minimum execution time) t inst 4/f ch , 8/f ch , 16/f ch , 64/f ch s (4/f ch )t inst = 0.32 s when operating at f ch = 12.5 mhz 2/f cl , 1/2f cl s (2/f cl )t inst = 61.036 s when operating at f cl = 32.768 khz x0a x1a c 0 c 1 rd open when a crystal or ceramic oscillator is used when subclock is not use d x0a x1a f cl 0.8 v cc t lcyl 0.2 v cc p whl p wll t cf t cr x 0a open when an external clock is used f cl x0a x1a sub-clock timing and conditions sub-clock conditions
33 mb89490 series relationship between subclock oscillating frequency and instruction cycle when subpll is enabled oscillation clock f cl (khz) instruction cylcle, t inst (min. exec. time) (us) multiplied- by-4 15.625 6.67 75 32.768 relationship between internal operating clock frequency and power supply voltage pll operation guarantee range 2.0 3.0 operating voltage (v) 3.6 2.7 300 6.67 2.5 min execution time (inst. cycle) ( s) internal operating clock freq. (khz) 131.072 subpll operating guarantee range 15.625 not assured for mb89f499, mb89pv490. (subpll x 4)
34 mb89490 series (5) serial i/o timing (av cc = v cc = 3.0 v, av ss = v ss = 0.0 v, t a = ?40 c to +85 c) * : for information on t inst , see ?(4) instruction cycle.? parameter symbol pin condition value unit min. max. serial clock cycle time t scyc sck0, sck1 internal shift clock mode 2 t inst *? s sck so time t slov sck0, sck1, so0, so1 ?200 200 ns valid si sck t ivsh si0, si1, sck0, sck1 1/2 t inst *? s sck valid si hold time t shix sck0, sck1, si0, si1 1/2 t inst *? s serial clock ?h? pulse width t shsl sck0, sck1 external shift clock mode 1 t inst *? s serial clock ?l? pulse width t slsh 1 t inst *? s sck so time t slov sck0, sck1, so0, so1 0 200 ns valid si sck t ivsh si0, si1, sck0, sck1 1/2 t inst *? s sck valid si hold time t shix sck0, sck1, si0, si1 1/2 t inst *? s 0.2 v cc 0.8 v cc t slsh 2.4 v 0.2 v cc 0.8 v cc 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc s ck0, sck1 so0, so1 si0, si1 0.2 v cc t shsl t shix t ivsh t slov external clock operation 0.8 v 2.4 v t scyc 2.4 v 0.2 v cc t shix 0.8 v 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc s ck0, sck1 so0, so1 si0, si1 t slov internal clock operation
35 mb89490 series (6) i 2 c timing (vcc = 3.0v, av ss = v ss = 0.0 v, t a = ?40 c to +85 c) *1: for information in t inst , see "(4) instruction cycle". *2: m is defined in the iccr cs4 and cs3 (bit 4 to bit 3). for details, please refer to the h/w manual register explanation. *3: n is defined in the iccr cs2 to cs0 (bit 2 to bit 0) *4: when the interrupt period is grater than scl "l" width, sda and scl output (standard) value is based on hypothesis when rising time is 0 ns. parameter symbol pin condition value unit remarks min. max. start condition output t sta scl sda 1/4t inst * 1 x m x n - 20 1/4t inst x m x n + 20 ns master mode stop condition output t sto scl sda 1/4t inst x (m x n + 8) - 20 1/4t inst x (m* 2 x n* 3 + 8) + 20 ns master mode start condition detect t sta scl sda 1/4t inst x 6 + 40 ? ns stop condition detect t sto scl sda 1/4t inst x 6 + 40 ? ns re-start condition output t stasu scl sda 1/4t inst x (m x n + 8) - 20 1/4t inst x (m x n + 8) + 20 ns master mode re-start condition detect t stasu scl sda 1/4t inst x 4 + 40 ? ns scl output low width t low scl 1/4t inst x m x n - 20 1/4t inst x m x n + 20 ns master mode scl output high width t high scl 1/4t inst x (m x n + 8) - 20 1/4t inst x (m x n + 8) + 20 ns master mode sda output delay t do sda 1/4t inst x 4 - 20 1/4t inst x 4 + 20 ns sda output setup time after interrupt t dosu sda 1/4t inst x 4 - 20 ? ns * 4 scl input low pulse width t low scl 1/4t inst x 6 + 40 ? ns scl input high pulse width t high scl 1/4 t inst x 2 + 40 ? ns sda input setup time t su sda 40 ? ns sda hold time t ho sda 0 ? ns sda scl sda scl 1 ack 9 67 8 9 t do t stasu t sta t low t ho t do t su t ho t dosu t su t ho t do t do t dosu t high t low t sto data transmit (master/slave) data receive (master/slave) ack
36 mb89490 series (7) peripheral input timing (av cc = v cc = 3.0 v, av ss = v ss = 0.0 v, t a = ?40 c to +85 c) * : for information on t inst, see ?(4) instruction cycle.? parameter symbol pin value unit remarks min. max. peripheral input ?h? pulse width 1 t ilih1 ec0, ec1, rmc, int00 ~ int07, int10 ~ int17 2 t inst *? s peripheral input ?l? pulse width 1 t ihil1 2 t inst *? s 0.2 v cc 0.8 v cc t ihil1 0.8 v cc e c0, ec1, rmc, i nt00 ~ int07 0.2 v cc t ilih1 0.5 v cc 0.85 v cc t ihil1 0.85 v cc i nt10 to int17 0.5 v cc t ilih1
37 mb89490 series 5. a/d converter electrical characteristics (1) a/d converter electrical characteristics (av cc = v cc = 2.7 v ~ 3.6 v, av ss = v ss = 0.0 v, t a = ?40 c to +85 c) * : for information on t inst , see "(4) instruction cycle" in "4. ac characteristics". (2) a/d converter glossary resolution analog changes that are identifiable with the a/d converter. when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. linearity error (unit: lsb) the deviation of the straight line connecting the zero transition point ("00 0000 0000" ? "00 0000 0001") with the full-scale transition point ("11 1111 1111" ? "11 1111 1110") from actual conversion characteristics. differential linearity error (unit: lsb) the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value. total error (unit: lsb) the difference between theoretical and actual conversion values. parameter symbol pin value unit remarks min. typ. max. resolution ? ? ?10 ?bit tota l e rr or ? ? 3.0 lsb linearity error ? ? 2.5 lsb differential linearity error ? ? 1.9 lsb zero transition voltage v ot av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full-scale transition voltage v fst av cc ? 3.5 lsb av cc ? 1.5 lsb av cc - 0.5 lsb mv a/d mode conversion time ? ? ? 38 tinst* s analog port input current i ain an0 to an7 ??10 a analog input voltage v ain av ss ? avr v reference voltage ? avr av ss + 2.7 ? av cc v reference voltage supply current i r ?200tbd a a/d is activated i rh ?? 5 a a/d is stopped
38 mb89490 series 0.5 lsb 1 lsb analog input av ss 1.5 lsb theoretical i/o characteristics 3ff 3fe 3fd 004 003 002 001 av cc theoretical value analog input av ss v nt actual conversion value total error 3ff 3fe 3fd 004 003 002 001 av c c {1 lsb n + v ot } v fst v ot actual conversion value total error = v nt ? {1 lsb n + 0.5 lsb} 1 lsb 1 lsb = v fst ? v ot 1022 digital output digital output (v) analog input av ss linearity error 3ff 3fe 3fd 004 003 002 001 av cc theoretical value analog input av ss v nt v (n + 1)t actual conversion value differential linearity error n + 1 n n ? 1 n ? 2 av c c v nt v ot (actual measurement) actual conversion value actual conversion value differential linearity error = 1 lsb v (n + 1)t ? v nt digital output digital output linearity error = v nt ? {1 lsb n + v ot } 1 lsb ? 1 {1 lsb n + v ot } actual conversion value v fst (actual measurement) theoretical value analog input av ss zero transition error 004 003 002 001 theoretical value analog input actual conversion value full-scale transition error av c c actual conversion value digital output digital output actual conversion value actual conversion value v ot (actual measurement) v fst (actual measurement) 3ff 3fe 3fd 3fc
39 mb89490 series (3) notes on using a/d converter input impedance of the analog input pins the a/d converter used for the mb89490 series contains a sample and hold circuit as illustrated below to fetch analog input voltage into the sample and hold capacitor for 16 instruction cycles after activation a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low . note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 f for the analog input pin. mb89f499 mb89pv490/mb89497/mb89498 r: analog input equivalent resistance 2.4 k ? 2.4 k ? c: analog input equivalent capacitance 52 pf 53 pf analog input pin sample hold circuit comparator r c analog channel selector close for 16 instruction cycles after activating a/d conversion. i f the analog input i mpedance is higher t han 10 k ? , it is r ecommended to c onnect an external c apacitor of approx. 0 .1 f. analog input circuit model
40 mb89490 series mask options no. part number mb89497 mb89498 mb89f499 mb89pv490 specifying procedure specify when ordering mask setting not possible 1 selection of oscillation stabilization time (osc) the initial value of the oscillation stabilization time for the main clock can be set by selecting the values of the wtm1 and wtm0 bit on the right. selectable osc 1 : 2 10 /f ch 2 : 2 14 /f ch 3 : 2 18 /f ch fixed to oscillation stabilization time of 2 18 /f ch
41 mb89490 series ordering information part number package remarks mb89497pf MB89498PF mb89f499pf 100-pin plastic qfp (fpt-100p-m06) mb89pv490cf 100-pin ceramic mqfp (mqp-100c-p01)
42 mb89490 series package dimensions (continued) c 2001 fujitsu limited f100008s-c-4-4 1 30 31 50 51 80 81 100 20.000.20(.787.008) 23.900.40(.941.016) 14.000.20 (.551.008) 17.900.40 (.705.016) index 0.65(.026) 0.320.05 (.013.002) m 0.13(.005) "a" 0.170.06 (.007.002) 0.10(.004) details of "a" part 0~8 (.035.006) 0.880.15 (.031.008) 0.800.20 0.25(.010) 3.00 +0.35 ?0.20 +.014 ?.008 .118 (mounting height) 0.250.20 (.010.008) (stand off) 100-pin plastic qfp fpt-100p-m06 dimensions in mm (inches)
43 mb89490 series (continued) c 1994 fujitsu limited m100001sc-1-2 15.580.20 (.613.008) 16.300.33 (.642.013) 18.70(.736)typ index area 0.30(.012) typ 1.270.13 (.050.005) 22.300.33 (.878.013) 24.70(.972) typ 10.16(.400) typ 12.02(.473) typ 14.22(.560) typ 18.120.20 (.713.008) 1.270.13 (.050.005) 0.30(.012)typ 7.62(.300)typ 9.48(.373)typ 11.68(.460)typ 0.150.05 (.006.002) 10.82(.426) max 0.300.08 (.012.003) .047 ?.008 +.016 ?0.20 +0.40 1.20 0.300.08 (.012.003) 0.650.15 (.0256.0060) 18.85(.742) typ 0.650.15 (.0256.0060) 12.35(.486)typ .047 ?.008 +.016 ?0.20 +0.40 1.20 100-pin ceramic mqfp mqp-100c-p01
44 mb89490 series memo
45 mb89490 series fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ f0208 fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed , developed and manufactured as contemplated for genera l use, including without limitation, ordinary industrial use , general office use, personal use, and household use, bu t are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured , could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and / or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance o f failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-curren t levels and other abnormal operating conditions. if any products described in this document represen t goods or technologies subject to certain restrictions on ex- port under the foreign exchange and foreign trade law of japan, the prior authorization by japanese governmen t will be required for export of those products from japan.

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